Move to PLLC because PLLA used by openvg
This commit is contained in:
F5OEO
parent
3da98b2e0f
commit
73f0ba145b
7 changed files with 130 additions and 49 deletions
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@ -48,7 +48,7 @@ void SimpleTest(uint64_t Freq)
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clkgpio clk;
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clk.print_clock_tree();
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clk.SetPllNumber(clk_plla,0);
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clk.SetPllNumber(clk_pllc,0);
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//clk.SetAdvancedPllMode(true);
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//clk.SetPLLMasterLoop(0,4,0);
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@ -189,41 +189,26 @@ void SimpleTestbpsk(uint64_t Freq)
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clkgpio clk;
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clk.print_clock_tree();
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int SR=100000;
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int FifoSize=1024;
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int SR=250000;
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int FifoSize=10000;
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int NumberofPhase=2;
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phasedmasync biphase(Freq,SR,NumberofPhase,14,FifoSize);
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padgpio pad;
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pad.setlevel(7);
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int lastphase=0;
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#define BURST_SIZE 100
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int PhaseBuffer[BURST_SIZE];
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while(running)
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{
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//usleep(FifoSize*1000000.0*1.0/(8.0*SR));
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usleep(10);
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int Available=biphase.GetBufferAvailable();
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if(Available>256)
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for(int i=0;i<BURST_SIZE;i++)
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{
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int Index=biphase.GetUserMemIndex();
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for(int i=0;i<Available;i++)
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{
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int phase=(rand()%NumberofPhase);
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biphase.SetPhase(Index+i,phase);
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}
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/*
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for(int i=0;i<Available/2;i++)
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{
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int phase=2*(rand()%NumberofPhase/2);
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biphase.SetPhase(Index+i*2,(phase+lastphase)/2);
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biphase.SetPhase(Index+i*2+1,phase);
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lastphase=phase;
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}*/
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/*for(int i=0;i<Available;i++)
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{
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lastphase=(lastphase+1)%NumberofPhase;
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biphase.SetPhase(Index+i,lastphase);
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}*/
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int phase=(rand()%NumberofPhase);
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PhaseBuffer[i]=phase;
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}
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biphase.SetPhaseSamples(PhaseBuffer,BURST_SIZE);
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}
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biphase.stop();
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}
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@ -408,9 +393,9 @@ int main(int argc, char* argv[])
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}
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//SimpleTest(Freq);
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//SimpleTestbpsk(Freq);
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SimpleTestbpsk(Freq);
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//SimpleTestFileIQ(Freq);
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SimpleTestDMA(Freq);
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//SimpleTestDMA(Freq);
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//SimpleTestAm(Freq);
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//SimpleTestOOK(Freq);
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//SimpleTestBurstFsk(Freq);
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@ -73,7 +73,7 @@ This program is free software: you can redistribute it and/or modify
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cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
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cbp->dst = 0x7E000000 + (PLLA_FRAC<<2) + CLK_BASE ;
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cbp->dst = 0x7E000000 + (PLLC_FRAC<<2) + CLK_BASE ;
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cbp->length = 4;
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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48
src/gpio.cpp
48
src/gpio.cpp
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@ -87,6 +87,7 @@ int clkgpio::SetPllNumber(int PllNo, int MashType)
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else
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Mash = 0;
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gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber /*|(1 << 5)*/; //5 is Reset CLK
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usleep(100);
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gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber /*|(1 << 5)*/; //5 is Reset CLK
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usleep(100);
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Pllfrequency = GetPllFrequency(pllnumber);
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@ -124,6 +125,7 @@ int clkgpio::SetClkDivFrac(uint32_t Div, uint32_t Frac)
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{
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gpioreg[GPCLK_DIV] = 0x5A000000 | ((Div) << 12) | Frac;
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usleep(100);
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gpioreg[GPCLK_DIV_2] = 0x5A000000 | ((Div) << 12) | Frac;
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usleep(100);
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fprintf(stderr, "Clk Number %d div %d frac %d\n", pllnumber, Div, Frac);
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@ -136,9 +138,9 @@ int clkgpio::SetMasterMultFrac(uint32_t Mult, uint32_t Frac)
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{
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//fprintf(stderr,"Master Mult %d Frac %d\n",Mult,Frac);
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gpioreg[PLLA_CTRL] = (0x5a << 24) | (0x21 << 12) | Mult; //PDIV=1
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gpioreg[PLLC_CTRL] = (0x5a << 24) | (0x21 << 12) | Mult; //PDIV=1
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usleep(100);
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gpioreg[PLLA_FRAC] = 0x5A000000 | Frac;
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gpioreg[PLLC_FRAC] = 0x5A000000 | Frac;
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return 0;
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}
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@ -300,18 +302,20 @@ int clkgpio::SetCenterFrequency(uint64_t Frequency, int Bandwidth)
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SetFrequency(0);
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usleep(1000);
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if ((gpioreg[CM_LOCK] & CM_LOCK_FLOCKA) > 0)
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fprintf(stderr, "Master PLLA Locked\n");
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if ((gpioreg[CM_LOCK] & CM_LOCK_FLOCKC) > 0)
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fprintf(stderr, "Master PLLC Locked\n");
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else
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fprintf(stderr, "Warning ! Master PLLA NOT Locked !!!!\n");
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fprintf(stderr, "Warning ! Master PLLC NOT Locked !!!!\n");
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SetClkDivFrac(PllFixDivider, 0x0); // NO MASH !!!!
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usleep(100);
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usleep(100);
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gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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usleep(100);
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gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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usleep(100);
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gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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usleep(100);
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gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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usleep(100);
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}
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@ -338,26 +342,44 @@ void clkgpio::SetAdvancedPllMode(bool Advanced)
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ModulateFromMasterPLL = Advanced;
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if (ModulateFromMasterPLL)
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{
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SetPllNumber(clk_plla, 0); // Use PPL_A , Do not USE MASH which generates spurious
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gpioreg[CM_PLLA] = 0x5A00022A; // Enable Plla_PER
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//We must change Clk dependant from PLLC as we will modulate it
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// switch the core over to PLLA
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gpioreg[CORECLK_DIV] = (0x5a<<24) | (4<<12) ; // core div 4
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usleep(100);
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gpioreg[CORECLK_CNTL] = (0x5a<<24) | (1<<4) | (4); // run, src=PLLA
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// switch the EMMC over to PLLD
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int clktmp;
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clktmp = gpioreg[EMMCCLK_CNTL];
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gpioreg[EMMCCLK_CNTL] = (0xF0F&clktmp) | (0x5a<<24) ; // clear run
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usleep(100);
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gpioreg[EMMCCLK_CNTL] = (0xF00&clktmp) | (0x5a<<24) | (6); // src=PLLD
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usleep(100);
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gpioreg[EMMCCLK_CNTL] = (0xF00&clktmp) | (0x5a<<24) | (1<<4) | (6); // run , src=PLLD
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SetPllNumber(clk_pllc, 0); // Use PLL_C , Do not USE MASH which generates spurious
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//gpioreg[CM_PLLA] = 0x5A00022A; // Enable PllA_PER
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gpioreg[CM_PLLC] = 0x5A00022A; // Enable PllA_PER
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usleep(100);
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uint32_t ana[4];
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for (int i = 3; i >= 0; i--)
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{
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ana[i] = gpioreg[(A2W_PLLA_ANA0 ) + i];
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ana[i] = gpioreg[(A2W_PLLC_ANA0 ) + i];
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}
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ana[1]&=~(1<<14); // No use prediv means Frequency
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//ana[1] |= (1 << 14); // use prediv means Frequency*2
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for (int i = 3; i >= 0; i--)
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{
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gpioreg[(A2W_PLLA_ANA0 ) + i] = (0x5A << 24) | ana[i];
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gpioreg[(A2W_PLLC_ANA0 ) + i] = (0x5A << 24) | ana[i];
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}
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usleep(100);
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gpioreg[PLLA_CORE] = 0x5A000000|(1<<8);//Disable
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gpioreg[PLLA_PER] = 0x5A000001; // Divisor
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gpioreg[PLLC_CORE0] = 0x5A000000|(1<<8);//Disable
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gpioreg[PLLC_PER] = 0x5A000001; // Divisor
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usleep(100);
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}
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}
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@ -367,14 +389,14 @@ void clkgpio::SetPLLMasterLoop(int Ki,int Kp,int Ka)
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uint32_t ana[4];
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for (int i = 3; i >= 0; i--)
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{
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ana[i] = gpioreg[(A2W_PLLA_ANA0 ) + i];
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ana[i] = gpioreg[(A2W_PLLC_ANA0 ) + i];
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}
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ana[1]=(Ki<<A2W_PLL_KI_SHIFT)|(Kp<<A2W_PLL_KP_SHIFT)|(Ka<<A2W_PLL_KA_SHIFT);
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fprintf(stderr,"Loop parameter =%x\n",ana[1]);
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for (int i = 3; i >= 0; i--)
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{
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gpioreg[(A2W_PLLA_ANA0 ) + i] = (0x5A << 24) | ana[i];
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gpioreg[(A2W_PLLC_ANA0 ) + i] = (0x5A << 24) | ana[i];
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}
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usleep(100) ;
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//Only PLLA for now
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74
src/gpio.h
74
src/gpio.h
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@ -97,6 +97,79 @@ class generalgpio:public gpio
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#define EMMCCLK_CNTL (0x1C0/4)
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#define EMMCCLK_DIV (0x1C4/4)
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#define CM_VPUCTL 0x008
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#define CM_VPUDIV 0x00c
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#define CM_SYSCTL 0x010
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#define CM_SYSDIV 0x014
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#define CM_PERIACTL 0x018
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#define CM_PERIADIV 0x01c
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#define CM_PERIICTL 0x020
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#define CM_PERIIDIV 0x024
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#define CM_H264CTL 0x028
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#define CM_H264DIV 0x02c
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#define CM_ISPCTL 0x030
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#define CM_ISPDIV 0x034
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#define CM_V3DCTL 0x038
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#define CM_V3DDIV 0x03c
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#define CM_CAM0CTL 0x040
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#define CM_CAM0DIV 0x044
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#define CM_CAM1CTL 0x048
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#define CM_CAM1DIV 0x04c
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#define CM_CCP2CTL 0x050
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#define CM_CCP2DIV 0x054
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#define CM_DSI0ECTL 0x058
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#define CM_DSI0EDIV 0x05c
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#define CM_DSI0PCTL 0x060
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#define CM_DSI0PDIV 0x064
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#define CM_DPICTL 0x068
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#define CM_DPIDIV 0x06c
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#define CM_GP0CTL 0x070
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#define CM_GP0DIV 0x074
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#define CM_GP1CTL 0x078
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#define CM_GP1DIV 0x07c
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#define CM_GP2CTL 0x080
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#define CM_GP2DIV 0x084
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#define CM_HSMCTL 0x088
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#define CM_HSMDIV 0x08c
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#define CM_OTPCTL 0x090
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#define CM_OTPDIV 0x094
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#define CM_PCMCTL 0x098
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#define CM_PCMDIV 0x09c
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#define CM_PWMCTL 0x0a0
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#define CM_PWMDIV 0x0a4
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#define CM_SLIMCTL 0x0a8
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#define CM_SLIMDIV 0x0ac
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#define CM_SMICTL 0x0b0
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#define CM_SMIDIV 0x0b4
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/* no definition for 0x0b8 and 0x0bc */
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#define CM_TCNTCTL 0x0c0
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# define CM_TCNT_SRC1_SHIFT 12
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#define CM_TCNTCNT 0x0c4
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#define CM_TECCTL 0x0c8
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#define CM_TECDIV 0x0cc
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#define CM_TD0CTL 0x0d0
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#define CM_TD0DIV 0x0d4
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#define CM_TD1CTL 0x0d8
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#define CM_TD1DIV 0x0dc
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#define CM_TSENSCTL 0x0e0
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#define CM_TSENSDIV 0x0e4
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#define CM_TIMERCTL 0x0e8
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#define CM_TIMERDIV 0x0ec
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#define CM_UARTCTL 0x0f0
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#define CM_UARTDIV 0x0f4
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#define CM_VECCTL 0x0f8
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#define CM_VECDIV 0x0fc
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#define CM_PULSECTL 0x190
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#define CM_PULSEDIV 0x194
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#define CM_SDCCTL 0x1a8
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#define CM_SDCDIV 0x1ac
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#define CM_ARMCTL 0x1b0
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#define CM_AVEOCTL 0x1b8
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#define CM_AVEODIV 0x1bc
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#define CM_EMMCCTL 0x1c0
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#define CM_EMMCDIV 0x1c4
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#define CM_LOCK (0x114/4)
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# define CM_LOCK_FLOCKH (1<<12)
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# define CM_LOCK_FLOCKD (1<<11)
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@ -170,6 +243,7 @@ class generalgpio:public gpio
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#define XOSC_CTRL (0x1190/4)
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#define XOSC_FREQUENCY 19200000
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//Parent PLL
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enum {clk_gnd,clk_osc,clk_debug0,clk_debug1,clk_plla,clk_pllc,clk_plld,clk_hdmi};
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class clkgpio:public gpio
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@ -96,7 +96,7 @@ void iqdmasync::SetDmaAlgo()
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cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
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cbp->dst = 0x7E000000 + (PLLA_FRAC<<2) + CLK_BASE ;
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cbp->dst = 0x7E000000 + (PLLC_FRAC<<2) + CLK_BASE ;
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cbp->length = 4;
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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@ -77,7 +77,7 @@ void ngfmdmasync::SetDmaAlgo()
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cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
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cbp->dst = 0x7E000000 + (PLLA_FRAC<<2) + CLK_BASE ;
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cbp->dst = 0x7E000000 + (PLLC_FRAC<<2) + CLK_BASE ;
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cbp->length = 4;
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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@ -28,7 +28,7 @@ phasedmasync::phasedmasync(uint64_t TuneFrequency,uint32_t SampleRateIn,int Numb
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{
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SampleRate=SampleRateIn;
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SetMode(pwm1pinrepeat);
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pwmgpio::SetPllNumber(clk_plla,0);
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pwmgpio::SetPllNumber(clk_pllc,0);
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tunefreq=TuneFrequency*NumberOfPhase;
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#define MAX_PWM_RATE 360000000
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